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Design of Area Efficient In-Memory Adder and Sum-Comparator with a Variable Reference Voltage Mechanism |
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Titel: |
Design of Area Efficient In-Memory Adder and Sum-Comparator with a Variable Reference Voltage Mechanism |
Auteur: |
Balasubramanian, Linknath Surya Racz, Elijah Eric Gopinath, Anoop Rizkalla, Maher Lee, John J. Ytterdal, Trond Kumar, Mukesh |
Verschenen in: |
Circuits, systems, and signal processing |
Paginering: |
Jaargang 44 () nr. 7 pagina's 5343-5356 |
Jaar: |
2025-03-06 |
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Uitgever: |
Springer US, New York |
Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
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