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Journal description
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Details for article 3 of 26 found articles
| Title: |
Analysis of Systolic Penalties and Design of Efficient Digit-Level Systolic-like Multiplier for Binary Extension Fields |
| Author: |
Meher, Bimal K. Meher, Pramod K. |
| Appeared in: |
Circuits, systems, and signal processing |
| Paging: | Volume 38 (2018) nr. 2 pages 774-790 |
| Year: |
2018 |
| Contents: | |
| Publisher: |
Springer US, New York |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 3 of 26 found articles
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