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  A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
 
 
Title: A 7.5 GS/s flash ADC and a 10.24 GS/s time-interleaved ADC for backplane receivers in 65 nm CMOS
Author: Chung, Hayun
Deniz, Zeynep Toprak
Rylyakov, Alexander
Bulzacchelli, John
Friedman, Daniel
Wei, Gu-Yeon
Appeared in: Analog integrated circuits and signal processing
Paging: Volume 85 (2015) nr. 2 pages 299-310
Year: 2015
Contents:
Publisher: Springer US, New York
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

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