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Journal description
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Details for article 10 of 14 found articles
| Title: |
A novel reversible gate and optimised implementation of half adder, subtractor and 2-bit multiplier |
| Author: |
Soyane, Siddhesh Kushwaha, Ajay Kumar Dhane, Dhiraj Manohar |
| Appeared in: |
Analog integrated circuits and signal processing |
| Paging: | Volume 118 () nr. 1 pages 171-186 |
| Year: |
2023-12-24 |
| Contents: | |
| Publisher: |
Springer US, New York |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 10 of 14 found articles
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