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Details for article 5 of 8 found articles
| Title: |
Design of a tunable delay line with on-chip calibration to generate process-invariant PWM signal for in-memory computing |
| Author: |
Monga, Kanika Shenoy, Meetha V. Chaturvedi, Nitin Gurunarayanan, S. |
| Appeared in: |
Analog integrated circuits and signal processing |
| Paging: | Volume 116 () nr. 1-2 pages 5-13 |
| Year: |
2023-06-28 |
| Contents: | |
| Publisher: |
Springer US, New York |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 5 of 8 found articles
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