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                                       Details for article 15 of 17 found articles
 
 
  TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power
 
 
Title: TSPC-HNTL: True Single Phase Clock technique for High speed, Noise Tolerance, and Low power
Author: Verma, Preeti
Sharma, Ajay K.
Pandey, Vinay S.
Noor, Arti
Appeared in: Analog integrated circuits and signal processing
Paging: Volume 112 () nr. 2 pages 333-345
Year: 2022-05-21
Contents:
Publisher: Springer US, New York
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 15 of 17 found articles
 
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 Koninklijke Bibliotheek - National Library of the Netherlands