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                                       Details for article 2 of 21 found articles
 
 
  A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL
 
 
Title: A low-jitter clock multiplier using a simple low-power ECDLL with extra settled delays in VCDL
Author: Sofimowloodi, Sobhan
Razaghian, Farhad
Gholami, Mohammad
Appeared in: Analog integrated circuits and signal processing
Paging: Volume 102 () nr. 3 pages 541-554
Year: 2020-02-04
Contents:
Publisher: Springer US, New York
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 2 of 21 found articles
 
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