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Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications |
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Titel: |
Digital-logic assessment of junctionless twin gate trench channel (JL-TGTC) MOSFET for memory circuit applications |
Auteur: |
Kumar, Ajay Gupta, Neha Jain, Aditya Gupta, Rajeev Choudhary, Bharat Kumar, Kaushal Goyal, Amit Kumar Massoud, Yehia |
Verschenen in: |
Memories, materials, devices, circuits and systems |
Paginering: |
Jaargang 6 () nr. C pagina's p. |
Jaar: |
2023 |
Inhoud: |
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Uitgever: |
The Authors |
Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
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