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                                       Details for article 2 of 28 found articles
 
 
  A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur
 
 
Title: A 5.7–6.0 GHz CMOS PLL with low phase noise and −68 dBc reference spur
Author: Li, Xiaoqiang
Zhang, Jingwei
Zhang, Yuanzhi
Wang, Wenshen
Liu, Huimin
Lu, Chao
Appeared in: A.E.Ü.
Paging: Volume 85 (2018) nr. C pages 23-31
Year: 2018
Contents:
Publisher: Elsevier GmbH
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 2 of 28 found articles
 
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 Koninklijke Bibliotheek - National Library of the Netherlands