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                                       Details for article 2 of 9 found articles
 
 
  ESD-level circuit simulation impact of interconnect RC-delay on HBM and CDM behavior
 
 
Title: ESD-level circuit simulation impact of interconnect RC-delay on HBM and CDM behavior
Author: Mergens, Markus P.J
Wilkening, Wolfgang
Kiesewetter, Gerhard
Mettler, Stephan
Wolf, Heinrich
Hieber, Jürgen
Fichtner, Wolfgang
Appeared in: Journal of electrostatics
Paging: Volume 54 (2002) nr. 1 pages 21 p.
Year: 2002
Contents:
Publisher: Elsevier Science B.V.
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 2 of 9 found articles
 
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 Koninklijke Bibliotheek - National Library of the Netherlands