|
| << previous | next >> |
Journal description
All volumes of the corresponding journal
All issues of the corresponding volume
All articles of the corresponding issues
Details for article 11 of 23 found articles
| Title: |
BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors |
| Author: |
Qiu, Keni Zhu, Yujie Xu, Yuanchao Huo, Qirun Xue, Chun Jason |
| Appeared in: |
Microelectronics journal |
| Paging: | Volume 83 () nr. C pages 137-146 |
| Year: |
2019 |
| Contents: | |
| Publisher: |
Elsevier Ltd |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 11 of 23 found articles
| << previous | next >> |