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Journal description
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Details for article 4 of 13 found articles
| Title: |
A power scalable 2–10 Gb/s PI-based clock data recovery for multilane applications |
| Author: |
Lv, Fangxu Zheng, Xuqiang Zhao, Feng Wang, Jianye Yue, Shigang Ziqiang Wang, Cao, Weidong He, Yajun Zhang, Chun Jiang, Hanjun Wang, Zhihua |
| Appeared in: |
Microelectronics journal |
| Paging: | Volume 82 () nr. C pages 36-45 |
| Year: |
2018 |
| Contents: | |
| Publisher: |
Elsevier Ltd |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 4 of 13 found articles
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