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  A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18µm CMOS
 
 
Title: A 12-bit 50MS/s zero-crossing-based two-stage pipelined SAR ADC in 0.18µm CMOS
Author: Shen, Yi
Liu, Shubin
Zhu, Zhangming
Appeared in: Microelectronics journal
Paging: Volume 57 () nr. C pages 26-33
Year: 2016
Contents:
Publisher: Elsevier Ltd
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

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