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                                       Details for article 13 of 17 found articles
 
 
  High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems
 
 
Title: High-speed hardware architecture of scalar multiplication for binary elliptic curve cryptosystems
Author: Rashidi, Bahram
Sayedi, Sayed Masoud
Farashahi, Reza Rezaeian
Appeared in: Microelectronics journal
Paging: Volume 52 () nr. C pages 49-65
Year: 2016
Contents:
Publisher: Elsevier Ltd
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 13 of 17 found articles
 
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 Koninklijke Bibliotheek - National Library of the Netherlands