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                                       Details for article 10 of 17 found articles
 
 
  FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
 
 
Title: FPGA based fast and high-throughput 2-slow retiming 128-bit AES encryption algorithm
Author: Farashahi, Reza Rezaeian
Rashidi, Bahram
Sayedi, Sayed Masoud
Appeared in: Microelectronics journal
Paging: Volume 45 () nr. 8 pages 1014-1025
Year: 2014
Contents:
Publisher: Elsevier Ltd
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 10 of 17 found articles
 
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