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                                       Details for article 106 of 127 found articles
 
 
  Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates
 
 
Title: Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates
Author: Rezaei, Siavash
Miremadi, Seyed Ghassem
Asadi, Hossein
Fazeli, Mahdi
Appeared in: Microelectronics reliability
Paging: Volume 54 (2014) nr. 6-7 pages 9 p.
Year: 2014
Contents:
Publisher: Elsevier Ltd
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 106 of 127 found articles
 
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