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                                       Details for article 11 of 21 found articles
 
 
  Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits
 
 
Title: Implementation of self-checking two-level combinational logic on FPGA and CPLD circuits
Author: Stojčev, Mile K
Djordjević, Goran Lj
Stanković, Tatjana R
Appeared in: Microelectronics reliability
Paging: Volume 44 (2004) nr. 1 pages 6 p.
Year: 2004
Contents:
Publisher: Elsevier Ltd
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 11 of 21 found articles
 
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