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                                       Details for article 13 of 19 found articles
 
 
  Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level
 
 
Title: Interface traps in the sub-3 nm technology node: A comprehensive analysis and benchmarking of negative capacitance FinFET and nanosheet FETs - A reliability perspective from device to circuit level
Author: Valasa, Sresta
Kotha, Venkata Ramakrishna
Vadthiya, Narendar
Appeared in: Microelectronics reliability
Paging: Volume 160 () nr. C pages p.
Year: 2024
Contents:
Publisher: Elsevier Ltd
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 13 of 19 found articles
 
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