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Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET |
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Title: |
Simulation of the effect of parasitic channel height on characteristics of stacked gate-all-around nanosheet FET |
Author: |
Choi, Yunho Lee, Kitae Yeon Kim, Kyoung Kim, Sihyun Lee, Junil Lee, Ryoongbin Kim, Hyun-Min Suh Song, Young Kim, Sangwan Lee, Jong-Ho Park, Byung-Gook |
Appeared in: |
Solid-state electronics |
Paging: |
Volume 164 () nr. C pages p. |
Year: |
2020 |
Contents: |
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Publisher: |
Published by Elsevier B.V. |
Source file: |
Elektronische Wetenschappelijke Tijdschriften |
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