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Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22nm all-last high-k/metal-gate pMOSFETs |
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Titel: |
Process optimizations to recessed e-SiGe source/drain for performance enhancement in 22nm all-last high-k/metal-gate pMOSFETs |
Auteur: |
Qin, Changliang Wang, Guilei Hong, Peizhen Liu, Jinbiao Yin, Huaxiang Yin, Haizhou Ma, Xiaolong Cui, Hushan Lu, Yihong Meng, Lingkuan Xiang, Jinjuan Zhong, Huicai Zhu, Huilong Xu, Qiuxia Li, Junfeng Yan, Jian Zhao, Chao Radamson, Henry H. |
Verschenen in: |
Solid-state electronics |
Paginering: |
Jaargang 123 (2016) nr. C pagina's 6 p. |
Jaar: |
2016 |
Inhoud: |
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Uitgever: |
Elsevier Ltd |
Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
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