| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
A Force-Directed Scheduling based architecture generation algorithm and design tool for FPGAs
|
Areno, Matthew
|
|
2010
|
|
2-3 |
p. 124-135
12 p.
|
artikel
|
| 2 |
A scalable organization for distributed directories
|
Ros, Alberto
|
|
2010
|
|
2-3 |
p. 77-87
11 p.
|
artikel
|
| 3 |
Composition-based Cache simulation for structure reorganization
|
Shin, Keoncheol
|
|
2010
|
|
2-3 |
p. 136-149
14 p.
|
artikel
|
| 4 |
Editorial board
|
|
|
2004
|
|
2-3 |
p. IFC-
1 p.
|
artikel
|
| 5 |
Editorial Board / Aims and Scope
|
|
|
2010
|
|
2-3 |
p. IFC-
1 p.
|
artikel
|
| 6 |
Editorial Board / Aims and Scope
|
|
|
2007
|
|
2-3 |
p. CO2-
1 p.
|
artikel
|
| 7 |
Efficient parallel multiplier in shifted polynomial basis
|
Negre, Christophe
|
|
2007
|
|
2-3 |
p. 109-116
8 p.
|
artikel
|
| 8 |
Embedded cryptographic hardware
|
Nedjah, Nadia
|
|
2007
|
|
2-3 |
p. 69-71
3 p.
|
artikel
|
| 9 |
Fast hardware for modular exponentiation with efficient exponent pre-processing
|
Nedjah, Nadia
|
|
2007
|
|
2-3 |
p. 99-108
10 p.
|
artikel
|
| 10 |
FPGA schemes for minimizing the power-throughput trade-off in executing the Advanced Encryption Standard algorithm
|
Van Dyken, Jason
|
|
2010
|
|
2-3 |
p. 116-123
8 p.
|
artikel
|
| 11 |
Guide for Authors
|
|
|
2004
|
|
2-3 |
p. 165-168
4 p.
|
artikel
|
| 12 |
Hardware acceleration of the Tate pairing on a genus 2 hyperelliptic curve
|
Ronan, Robert
|
|
2007
|
|
2-3 |
p. 85-98
14 p.
|
artikel
|
| 13 |
High-speed hardware implementations of Elliptic Curve Cryptography: A survey
|
Meurice de Dormale, Guerric
|
|
2007
|
|
2-3 |
p. 72-84
13 p.
|
artikel
|
| 14 |
Interconnect intellectual property for Network-on-Chip (NoC)
|
Liu, Jian
|
|
2004
|
|
2-3 |
p. 65-79
15 p.
|
artikel
|
| 15 |
Multi-level reconfigurable architectures in the switch model
|
Lange, Sebastian
|
|
2010
|
|
2-3 |
p. 103-115
13 p.
|
artikel
|
| 16 |
Multi-mode operator for SHA-2 hash functions
|
Glabb, Ryan
|
|
2007
|
|
2-3 |
p. 127-138
12 p.
|
artikel
|
| 17 |
OCCN: a NoC modeling framework for design exploration
|
Coppola, Marcello
|
|
2004
|
|
2-3 |
p. 129-163
35 p.
|
artikel
|
| 18 |
Packetization and routing analysis of on-chip multiprocessor networks
|
Ye, Terry Tao
|
|
2004
|
|
2-3 |
p. 81-104
24 p.
|
artikel
|
| 19 |
QNoC: QoS architecture and design process for network on chip
|
Bolotin, Evgeny
|
|
2004
|
|
2-3 |
p. 105-128
24 p.
|
artikel
|
| 20 |
Robust codes and robust, fault-tolerant architectures of the Advanced Encryption Standard
|
Kulikowski, Konrad J.
|
|
2007
|
|
2-3 |
p. 139-149
11 p.
|
artikel
|
| 21 |
Scalable hardware implementing high-radix Montgomery multiplication algorithm
|
Bernard, F.
|
|
2007
|
|
2-3 |
p. 117-126
10 p.
|
artikel
|
| 22 |
Special issue on networks on chip
|
Jantsch, Axel
|
|
2004
|
|
2-3 |
p. 61-63
3 p.
|
artikel
|
| 23 |
UML-based hardware/software co-design platform for dynamically partially reconfigurable network security systems
|
Huang, Chun-Hsian
|
|
2010
|
|
2-3 |
p. 88-102
15 p.
|
artikel
|
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