| nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
| 1 |
Access to rows and columns of a rectangular array in a concentricloop bubble memory
|
Luccio, Fabrizio
|
|
1985
|
|
4 |
p. 347-354
8 p.
|
artikel
|
| 2 |
A comprehensive performance macro-modeling of on-chip RC interconnects considering line shielding effects
|
Engels, S.
|
|
2006
|
|
4 |
p. 433-456
24 p.
|
artikel
|
| 3 |
A coupling and crosstalk-considered timing-driven global routing algorithm for high-performance circuit design
|
Xu, Jingyu
|
|
2006
|
|
4 |
p. 457-473
17 p.
|
artikel
|
| 4 |
Active mode leakage reduction using fine-grained forward body biasing strategy
|
Khandelwal, Vishal
|
|
2007
|
|
4 |
p. 561-570
10 p.
|
artikel
|
| 5 |
A digital array based bit serial processor for arbitrary window size kernel convolution in vision sensors
|
Habibi, Mehdi
|
|
2014
|
|
4 |
p. 417-430
14 p.
|
artikel
|
| 6 |
A fast pipelined multi-mode DES architecture operating in IP representation
|
Guilley, Sylvain
|
|
2007
|
|
4 |
p. 479-489
11 p.
|
artikel
|
| 7 |
A gate-delay model focusing on current fluctuation over wide range of process–voltage–temperature variations
|
Shinkai, Ken-ichi
|
|
2013
|
|
4 |
p. 345-358
14 p.
|
artikel
|
| 8 |
A low-power oriented architecture for H.264 variable block size motion estimation based on a resource sharing scheme
|
Elhaji, Majdi
|
|
2013
|
|
4 |
p. 404-412
9 p.
|
artikel
|
| 9 |
A memory efficient parallel layered QC-LDPC decoder for CMMB systems
|
Li, Jiangpeng
|
|
2013
|
|
4 |
p. 359-368
10 p.
|
artikel
|
| 10 |
A modem in CMOS technology for data communication on the low-voltage power line
|
Guerra, O.
|
|
2003
|
|
4 |
p. 229-236
8 p.
|
artikel
|
| 11 |
An accurate sparse-matrix based framework for statistical static timing analysis
|
Ramalingam, Anand
|
|
2012
|
|
4 |
p. 365-375
11 p.
|
artikel
|
| 12 |
Analog and mixed-signal IC design and design methodologies
|
Fernández, Francisco V.
|
|
2003
|
|
4 |
p. 157-159
3 p.
|
artikel
|
| 13 |
Analysis and architecture design of scalable fractional motion estimation for H.264 encoding
|
Vasiljevic, Jasmina
|
|
2012
|
|
4 |
p. 427-438
12 p.
|
artikel
|
| 14 |
Analysis of missing and additional cell defects in sequential quantum-dot cellular automata
|
Huang, J.
|
|
2007
|
|
4 |
p. 503-515
13 p.
|
artikel
|
| 15 |
An analysis of ternary simulation as a tool for race detection in digital MOS circuits
|
Lengauer, T.
|
|
1986
|
|
4 |
p. 309-330
22 p.
|
artikel
|
| 16 |
An architecture for a VLSI FFT processor
|
Ja'Ja', Joseph
|
|
1983
|
|
4 |
p. 305-316
12 p.
|
artikel
|
| 17 |
An area-time efficient NMOS adder
|
Bayoumi, M.A.
|
|
1983
|
|
4 |
p. 317-334
18 p.
|
artikel
|
| 18 |
An efficient multiplier-less architecture for 2-D convolution with quadrant symmetric kernels
|
Zhang, Ming Z.
|
|
2007
|
|
4 |
p. 490-502
13 p.
|
artikel
|
| 19 |
An O(n) algorithm for width determination of power/ground routes for VLSI circuits
|
Chowdhury, S.
|
|
1986
|
|
4 |
p. 345-355
11 p.
|
artikel
|
| 20 |
A novel IEEE rounding algorithm for high-speed floating-point multipliers
|
Gök, Mustafa
|
|
2007
|
|
4 |
p. 549-560
12 p.
|
artikel
|
| 21 |
A novel low-power full-adder cell for low voltage
|
Navi, Keivan
|
|
2009
|
|
4 |
p. 457-467
11 p.
|
artikel
|
| 22 |
A novel net-degree distribution model and its application to floorplanning benchmark generation
|
Wan, Tao
|
|
2007
|
|
4 |
p. 420-433
14 p.
|
artikel
|
| 23 |
A parameterized graph-based framework for high-level test synthesis
|
Safari, Saeed
|
|
2006
|
|
4 |
p. 363-381
19 p.
|
artikel
|
| 24 |
A power efficient and simple scheme for dynamically biasing cascode amplifiers and telescopic op-amps
|
Ramírez-Angulo, Jaime
|
|
2008
|
|
4 |
p. 539-543
5 p.
|
artikel
|
| 25 |
APWL-Y: An accurate and efficient wirelength estimation technique for hexagon/triangle placement
|
Wei, Yaoguang
|
|
2007
|
|
4 |
p. 406-419
14 p.
|
artikel
|
| 26 |
Area-time efficient end-around inverted carry adders
|
Vergos, H.T.
|
|
2012
|
|
4 |
p. 388-394
7 p.
|
artikel
|
| 27 |
A simple built-in current sensor for I DDQ testing of CMOS data converters
|
Srivastava, A.
|
|
2005
|
|
4 |
p. 579-596
18 p.
|
artikel
|
| 28 |
A single-chip adaptive delta modulator with optimum performance
|
Kanopoulos, N.
|
|
1985
|
|
4 |
p. 319-328
10 p.
|
artikel
|
| 29 |
A systolic VLSI matrix for a family of fundamental searching problems
|
Halaas, Arne
|
|
1983
|
|
4 |
p. 269-282
14 p.
|
artikel
|
| 30 |
Author Index
|
|
|
2003
|
|
4 |
p. 263-264
2 p.
|
artikel
|
| 31 |
Author Index Volume
|
|
|
2005
|
|
4 |
p. 615-618
4 p.
|
artikel
|
| 32 |
Author Index Volume
|
|
|
2004
|
|
4 |
p. 353-354
2 p.
|
artikel
|
| 33 |
Author Index Volume 39
|
|
|
2006
|
|
4 |
p. 477-479
3 p.
|
artikel
|
| 34 |
Automatic generation of defect injectable VHDL fault models for ASIC standard cell libraries
|
Shaw, Donald
|
|
2006
|
|
4 |
p. 382-406
25 p.
|
artikel
|
| 35 |
Automation of clock distribution network design for digital integrated circuits using divide and conquer technique
|
Gupta, Anu
|
|
2006
|
|
4 |
p. 407-419
13 p.
|
artikel
|
| 36 |
Automation of IP qualification and IP exchange
|
Vörg, Andreas
|
|
2004
|
|
4 |
p. 323-352
30 p.
|
artikel
|
| 37 |
A variable frequency link for a power-aware network-on-chip (NoC)
|
Lee, Seung Eun
|
|
2009
|
|
4 |
p. 479-485
7 p.
|
artikel
|
| 38 |
Bus-driven floorplanning with bus pin assignment and deviation minimization
|
Wu, Po-Hsun
|
|
2012
|
|
4 |
p. 405-426
22 p.
|
artikel
|
| 39 |
Bus-driven floorplanning with thermal consideration
|
Wu, Po-Hsun
|
|
2013
|
|
4 |
p. 369-381
13 p.
|
artikel
|
| 40 |
Call for paper:Radio Frequency Integrated Circuit (RFIC) Design Techniques
|
|
|
2014
|
|
4 |
p. III-
1 p.
|
artikel
|
| 41 |
Call for papers
|
|
|
1986
|
|
4 |
p. 366-367
2 p.
|
artikel
|
| 42 |
Call for papers
|
|
|
1983
|
|
4 |
p. 365-367
3 p.
|
artikel
|
| 43 |
Call for papers
|
|
|
1984
|
|
4 |
p. 365-367
3 p.
|
artikel
|
| 44 |
Call for papers
|
|
|
1985
|
|
4 |
p. 363-366
4 p.
|
artikel
|
| 45 |
Call for paper: Special Issue On Application and Domain-Specific Computing
|
|
|
2014
|
|
4 |
p. II-
1 p.
|
artikel
|
| 46 |
Call for paper:Special Issue on Design Automation for Microfluidic-Based Biochips
|
|
|
2014
|
|
4 |
p. IV-
1 p.
|
artikel
|
| 47 |
Call for paper:Special Issue on VLSI Physical Design
|
|
|
2014
|
|
4 |
p. I-
1 p.
|
artikel
|
| 48 |
Canadian Microelectronics Corporation awards chip design and testing stations
|
|
|
1984
|
|
4 |
p. 357-
1 p.
|
artikel
|
| 49 |
Capacitor matching insensitive algorithmic ADC requiring no calibrations
|
Quinn, Patrick
|
|
2003
|
|
4 |
p. 211-228
18 p.
|
artikel
|
| 50 |
Characterization, testing and reconfiguration of faults in mesh networks
|
Maity, Soumen
|
|
2007
|
|
4 |
p. 525-535
11 p.
|
artikel
|
| 51 |
Compacted channel routing with via placement restrictions
|
Wong, D.F.
|
|
1986
|
|
4 |
p. 287-307
21 p.
|
artikel
|
| 52 |
Compact low-power implementation for continuous-time ΣΔ modulators
|
López-Morillo, E.
|
|
2013
|
|
4 |
p. 441-448
8 p.
|
artikel
|
| 53 |
Component placement in VLSI circuits using a constant pressure Monte Carlo method
|
Gay, J.G.
|
|
1985
|
|
4 |
p. 271-282
12 p.
|
artikel
|
| 54 |
Contents of volume 1
|
|
|
1983
|
|
4 |
p. 368-370
3 p.
|
artikel
|
| 55 |
Contents of volume 2
|
|
|
1984
|
|
4 |
p. 368-370
3 p.
|
artikel
|
| 56 |
Contents of volume 4
|
|
|
1986
|
|
4 |
p. 368-370
3 p.
|
artikel
|
| 57 |
Contents of volume 3
|
|
|
1985
|
|
4 |
p. 367-369
3 p.
|
artikel
|
| 58 |
Contents Volume
|
|
|
2003
|
|
4 |
p. 265-266
2 p.
|
artikel
|
| 59 |
Contents Volume
|
|
|
2005
|
|
4 |
p. 619-621
3 p.
|
artikel
|
| 60 |
Contents Volume
|
|
|
2004
|
|
4 |
p. 355-356
2 p.
|
artikel
|
| 61 |
Contents Volume 39
|
|
|
2006
|
|
4 |
p. 480-481
2 p.
|
artikel
|
| 62 |
Design and design methods for unified multiplier and inverter and its application for HECC
|
Fan, Junfeng
|
|
2011
|
|
4 |
p. 280-289
10 p.
|
artikel
|
| 63 |
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths
|
Xydis, Sotiris
|
|
2009
|
|
4 |
p. 486-503
18 p.
|
artikel
|
| 64 |
Design methodology for full custom CMOS microcomputers
|
Piguet, C.
|
|
1983
|
|
4 |
p. 335-350
16 p.
|
artikel
|
| 65 |
Design of a systolic-pipelined architecture for real-time enhancement of color video stream based on an illuminance–reflectance model
|
Ngo, Hau T.
|
|
2008
|
|
4 |
p. 474-488
15 p.
|
artikel
|
| 66 |
Edge layer embedding algorithm for mitigating on-package variation in 3D clock tree synthesis
|
Park, Sangdo
|
|
2014
|
|
4 |
p. 476-486
11 p.
|
artikel
|
| 67 |
Editorial
|
Spaanenburg, L.
|
|
1983
|
|
4 |
p. 267-
1 p.
|
artikel
|
| 68 |
Editorial
|
Spaanenburg, L.
|
|
1985
|
|
4 |
p. 269-
1 p.
|
artikel
|
| 69 |
Editorial
|
Spaanenburg, L.
|
|
1984
|
|
4 |
p. 277-
1 p.
|
artikel
|
| 70 |
Editorial
|
Spaanenburg, L.
|
|
1986
|
|
4 |
p. 285-
1 p.
|
artikel
|
| 71 |
Editorial Board
|
|
|
2003
|
|
4 |
p. v-vi
nvt p.
|
artikel
|
| 72 |
Efficient architecture and hardware implementation of hybrid fuzzy-Kalman filter for workload prediction
|
Kuang, Shiann-Rong
|
|
2014
|
|
4 |
p. 408-416
9 p.
|
artikel
|
| 73 |
Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
|
Sun, Yang
|
|
2011
|
|
4 |
p. 305-315
11 p.
|
artikel
|
| 74 |
Electromigration-aware analog Router with multilayer multiport terminal structures
|
Martins, Ricardo
|
|
2014
|
|
4 |
p. 532-547
16 p.
|
artikel
|
| 75 |
Enhancement of test data compression with multistage encoding
|
Sivanantham, S.
|
|
2014
|
|
4 |
p. 499-509
11 p.
|
artikel
|
| 76 |
Erratum to: “High-speed systolic architectures for finite field inversion” [Integration 38(3) (2005) 383–398]
|
Yan, Z.
|
|
2006
|
|
4 |
p. 474-476
3 p.
|
artikel
|
| 77 |
ESPRIT is almost here!
|
|
|
1983
|
|
4 |
p. 355-356
2 p.
|
artikel
|
| 78 |
European Conference on Electronic Design Automation EDA84
|
|
|
1983
|
|
4 |
p. 358-360
3 p.
|
artikel
|
| 79 |
Events
|
|
|
1986
|
|
4 |
p. 362-365
4 p.
|
artikel
|
| 80 |
Events
|
|
|
1984
|
|
4 |
p. 361-365
5 p.
|
artikel
|
| 81 |
Events
|
|
|
1985
|
|
4 |
p. 359-363
5 p.
|
artikel
|
| 82 |
Events
|
|
|
1983
|
|
4 |
p. 363-364
2 p.
|
artikel
|
| 83 |
Fast, compact and symmetric modular exponentiation architecture by common-multiplicand Montgomery modular multiplications
|
Wu, Tao
|
|
2013
|
|
4 |
p. 323-332
10 p.
|
artikel
|
| 84 |
Fast timing analysis of clock networks considering environmental uncertainty
|
Wang, Hai
|
|
2012
|
|
4 |
p. 376-387
12 p.
|
artikel
|
| 85 |
Fault-tolerant analysis of TMR design with noise-aware logic
|
Yan, Jin-Tai
|
|
2014
|
|
4 |
p. 452-460
9 p.
|
artikel
|
| 86 |
FROSTY: A program for fast extraction of high-level structural representation from circuit description for industrial CMOS circuits
|
Yang, Lei
|
|
2006
|
|
4 |
p. 311-339
29 p.
|
artikel
|
| 87 |
Full-chip leakage analysis for 65nm CMOS technology and beyond
|
Xue, Jiying
|
|
2010
|
|
4 |
p. 353-364
12 p.
|
artikel
|
| 88 |
Generic integration infrastructure for IP-based design processes and tools with a unified XML format
|
Visarius, Markus
|
|
2004
|
|
4 |
p. 289-321
33 p.
|
artikel
|
| 89 |
Handling routability in floorplan design with twin binary trees
|
Lai, Steve T.W.
|
|
2009
|
|
4 |
p. 449-456
8 p.
|
artikel
|
| 90 |
Hardware architectures for algebra, cryptology, and number theory
|
Gaj, Kris
|
|
2011
|
|
4 |
p. 257-258
2 p.
|
artikel
|
| 91 |
Hardware-efficient common-feedback Markov-random-field probabilistic-based noise-tolerant VLSI circuits
|
Wey, I-Chyn
|
|
2014
|
|
4 |
p. 431-442
12 p.
|
artikel
|
| 92 |
Hardware SLE solvers: Efficient building blocks for cryptographic and cryptanalyticapplications
|
Rupp, Andy
|
|
2011
|
|
4 |
p. 290-304
15 p.
|
artikel
|
| 93 |
Heuristic circuit simulation using PROLOG
|
Gullichsen, Eric
|
|
1985
|
|
4 |
p. 283-318
36 p.
|
artikel
|
| 94 |
High-level parameterizable area estimation modeling for ASIC designs
|
Eerola, Ville
|
|
2014
|
|
4 |
p. 461-475
15 p.
|
artikel
|
| 95 |
High performance set associative translation lookaside buffers for low power microprocessors
|
Haigh, Jonathan R.
|
|
2008
|
|
4 |
p. 509-523
15 p.
|
artikel
|
| 96 |
IMS opens its door
|
|
|
1986
|
|
4 |
p. 357-
1 p.
|
artikel
|
| 97 |
Integrating firewire peripheral interface with an ethernet custom network processor
|
Elkeelany, O.
|
|
2007
|
|
4 |
p. 536-548
13 p.
|
artikel
|
| 98 |
Intelligent IP retrieval driven by application requirements
|
Schaaf, Martin
|
|
2004
|
|
4 |
p. 253-287
35 p.
|
artikel
|
| 99 |
International Zürich Seminar on Digital Communications
|
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|
1983
|
|
4 |
p. 356-357
2 p.
|
artikel
|
| 100 |
INVOMEC for very large scale education
|
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|
1985
|
|
4 |
p. 356-
1 p.
|
artikel
|
| 101 |
IP and design reuse
|
Rosenstiel, Wolfgang
|
|
2004
|
|
4 |
p. 191-192
2 p.
|
artikel
|
| 102 |
IPRAIL—intellectual property reuse-based analog IC layout automation
|
Jangkrajarng, Nuttorn
|
|
2003
|
|
4 |
p. 237-262
26 p.
|
artikel
|
| 103 |
ISGP: Iterative sequential geometric programming for precise and robust CMOS analog circuit sizing
|
Kundu, Sudip
|
|
2014
|
|
4 |
p. 510-531
22 p.
|
artikel
|
| 104 |
LFSR multipliers over GF(2 m ) defined by all-one polynomial
|
Kim, Hyun-Sung
|
|
2007
|
|
4 |
p. 473-478
6 p.
|
artikel
|
| 105 |
Low area/power decimal addition with carry-select correction and carry-select sum-digits
|
Dorrigiv, Morteza
|
|
2014
|
|
4 |
p. 443-451
9 p.
|
artikel
|
| 106 |
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
|
Azizi Mazreah, Arash
|
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2013
|
|
4 |
p. 413-426
14 p.
|
artikel
|
| 107 |
Low-power compact composite field AES S-Box/Inv S-Box design in 65nm CMOS using Novel XOR Gate
|
Ahmad, Nabihah
|
|
2013
|
|
4 |
p. 333-344
12 p.
|
artikel
|
| 108 |
Low-power design techniques for low-voltage fast-settling operational amplifiers in switched-capacitor applications
|
Lotfi, Reza
|
|
2003
|
|
4 |
p. 175-189
15 p.
|
artikel
|
| 109 |
Low power dynamic logic circuit design using a pseudo dynamic buffer
|
Tang, Fang
|
|
2012
|
|
4 |
p. 395-404
10 p.
|
artikel
|
| 110 |
Low-power multi-core ATPG to target concurrency
|
Abdulrahman, Arkan
|
|
2008
|
|
4 |
p. 459-473
15 p.
|
artikel
|
| 111 |
Maximizing pin alignment by pin permutations
|
Schlag, M.D.F.
|
|
1984
|
|
4 |
p. 279-307
29 p.
|
artikel
|
| 112 |
Microelectronic architectures and devices for signal and symbol processing
|
Cavin III, R.K.
|
|
1983
|
|
4 |
p. 283-304
22 p.
|
artikel
|
| 113 |
Modeling and design of CMOS analog circuits through hierarchical abstraction
|
Dam, Samiran
|
|
2013
|
|
4 |
p. 449-462
14 p.
|
artikel
|
| 114 |
Multi-layer floorplanning for stacked ICs: Configuration number and fixed-outline constraints
|
Chen, Song
|
|
2010
|
|
4 |
p. 378-388
11 p.
|
artikel
|
| 115 |
Multilevel routing with jumper insertion for antenna avoidance
|
Ho, Tsung-Yi
|
|
2006
|
|
4 |
p. 420-432
13 p.
|
artikel
|
| 116 |
Multiplierless implementation of 2-D FIR filters
|
Yurdakul, Arda
|
|
2005
|
|
4 |
p. 597-613
17 p.
|
artikel
|
| 117 |
Novel state minimization and state assignment in finite state machine design for low-power portable devices
|
Shiue, Wen-Tsong
|
|
2005
|
|
4 |
p. 549-570
22 p.
|
artikel
|
| 118 |
On improving the quality of simple graphics
|
Edward, L.N.M.
|
|
1984
|
|
4 |
p. 349-355
7 p.
|
artikel
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