nr |
titel |
auteur |
tijdschrift |
jaar |
jaarg. |
afl. |
pagina('s) |
type |
1 |
A fast general slew constrained minimum cost buffering algorithm
|
Hu, Shiyan |
|
2009 |
40 |
10 |
p. 1482-1486 5 p. |
artikel |
2 |
A fully redundant decimal adder and its application in parallel decimal multipliers
|
Gorgin, Saeid |
|
2009 |
40 |
10 |
p. 1471-1481 11 p. |
artikel |
3 |
A novel low-power full-adder cell with new technique in designing logical gates based on static CMOS inverter
|
Navi, K. |
|
2009 |
40 |
10 |
p. 1441-1448 8 p. |
artikel |
4 |
A 30pA/V– 25 μ A / V linear CMOS channel-length-modulation OTA
|
Huang, Yan |
|
2009 |
40 |
10 |
p. 1458-1465 8 p. |
artikel |
5 |
A systematic design approach for low-power 10-bit 100MS/s pipelined ADC
|
Meganathan, D. |
|
2009 |
40 |
10 |
p. 1417-1435 19 p. |
artikel |
6 |
A wide dynamic range CMOS image sensor with pulse-frequency-modulation and in-pixel amplification
|
Chen, Yong |
|
2009 |
40 |
10 |
p. 1496-1501 6 p. |
artikel |
7 |
CMOS voltage-mode quaternary look-up tables for multi-valued FPGAs
|
da Silva, R.C.G. |
|
2009 |
40 |
10 |
p. 1466-1470 5 p. |
artikel |
8 |
Design-for-testability techniques for CORDIC design
|
Ye, Bo-Yuan |
|
2009 |
40 |
10 |
p. 1436-1440 5 p. |
artikel |
9 |
Editorial board
|
|
|
2009 |
40 |
10 |
p. IFC- 1 p. |
artikel |
10 |
FIR filter optimization using bit-edge equalization in high-speed backplane data transmission
|
Zhang, Lei |
|
2009 |
40 |
10 |
p. 1449-1457 9 p. |
artikel |
11 |
Low-power and high-performance techniques in global interconnect signaling
|
Moghaddam Tabrizi, Mohammad |
|
2009 |
40 |
10 |
p. 1487-1495 9 p. |
artikel |