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                             20 results found
no title author magazine year volume issue page(s) type
1 A high level synthesis design flow with a novel approach for efficient design space exploration in case of multi-parametric optimization objective Sengupta, Anirban
2010
50 3 p. 424-437
14 p.
article
2 Analysis of dependence of short-channel effects in double-gate MOSFETs on channel thickness Kobayashi, Yusuke
2010
50 3 p. 332-337
6 p.
article
3 A prognostics and health management roadmap for information and electronics-rich systems Pecht, Michael
2010
50 3 p. 317-323
7 p.
article
4 Calendar 2010
50 3 p. I-III
nvt p.
article
5 Circuit level interconnect reliability study using 3D circuit model He, Feifei
2010
50 3 p. 376-390
15 p.
article
6 Electromigration-induced stress in a confined bamboo interconnect with randomly distributed grain sizes Dong, X.
2010
50 3 p. 391-397
7 p.
article
7 Electro-thermal stress effect on InGaP/GaAs heterojunction bipolar low-noise amplifier performance Liu, Xiang
2010
50 3 p. 365-369
5 p.
article
8 Extraction of VBIC model parameters for InGaAsSb DHBTs Chang, Yang-Hua
2010
50 3 p. 370-375
6 p.
article
9 Impact of interface state trap density on the performance characteristics of different III–V MOSFET architectures Benbakhti, B.
2010
50 3 p. 360-364
5 p.
article
10 Improved resolution method to study at 3D the conduction phenomena inside GaAs PIN photodiode Bouabdallah, B.
2010
50 3 p. 447-453
7 p.
article
11 Inside front cover - Editorial board 2010
50 3 p. IFC-
1 p.
article
12 Modeling of drain current, capacitance and transconductance in thin film undoped symmetric DG MOSFETs including quantum effects Mohammadi, Saeed
2010
50 3 p. 338-345
8 p.
article
13 Observation of halo implant from the drain side reaching the source side and vice versa in extremely short p-channel transistors Lau, W.S.
2010
50 3 p. 346-350
5 p.
article
14 Reliability enhancement of digital combinational circuits based on evolutionary approach Seyyed Mahdavi, S.J.
2010
50 3 p. 415-423
9 p.
article
15 Reliability growth modeling for in-service electronic systems considering latent failure modes Jin, Tongdan
2010
50 3 p. 324-331
8 p.
article
16 Reliability Object Model Tree (ROM-Tree): A system design-for-reliability method Kim, Injoong
2010
50 3 p. 438-446
9 p.
article
17 SrO capping effect for La2O3/Ce-silicate gate dielectrics Kakushima, K.
2010
50 3 p. 356-359
4 p.
article
18 The frequency-dependent electrical characteristics of interfaces in the Sn/p-Si metal semiconductor structures Karataş, Ş.
2010
50 3 p. 351-355
5 p.
article
19 The use of Mahalanobis–Taguchi System to improve flip-chip bumping height inspection efficiency Yang, Taho
2010
50 3 p. 407-414
8 p.
article
20 Warpage mechanism analyses of strip panel type PBGA chip packaging Kim, Yeong K.
2010
50 3 p. 398-406
9 p.
article
                             20 results found
 
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