| no |
title |
author |
magazine |
year |
volume |
issue |
page(s) |
type |
| 1 |
Advanced 2D/3D ESD device simulation – a powerful tool already used in a pre-Si phase
|
Esmark, K
|
|
2001
|
41 |
11 |
p. 1761-1770
10 p.
|
article
|
| 2 |
A method of thermal testing of microsystems
|
Bratek, Piotr
|
|
2001
|
41 |
11 |
p. 1877-1887
11 p.
|
article
|
| 3 |
An assessment of the value of added screening of electronic components for commercial aerospace applications
|
Hester, Kendall D
|
|
2001
|
41 |
11 |
p. 1823-1828
6 p.
|
article
|
| 4 |
A new lifetime prediction method for hot-carrier degradation in n-MOSFETs with ultrathin gate oxides under V g=V d
|
Mu, Fuchen
|
|
2001
|
41 |
11 |
p. 1909-1913
5 p.
|
article
|
| 5 |
Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions
|
Wu, J
|
|
2001
|
41 |
11 |
p. 1771-1779
9 p.
|
article
|
| 6 |
Distributed control based on distributed electronic circuits: application to vibration control
|
Kader, Mahamane
|
|
2001
|
41 |
11 |
p. 1857-1866
10 p.
|
article
|
| 7 |
Effect of SiO2/Si interface roughness on gate current
|
Mao, Ling-Feng
|
|
2001
|
41 |
11 |
p. 1903-1907
5 p.
|
article
|
| 8 |
Effects of thermomechanical cycling on lead and lead-free (SnPb and SnAgCu) surface mount solder joints
|
Stam, F.A.
|
|
2001
|
41 |
11 |
p. 1815-1822
8 p.
|
article
|
| 9 |
Electrical degradation and recovery of dielectrics in n++-poly-Si/SiO x /SiO2/p-sub structures designed for application in low-voltage non-volatile memories
|
Irrera, Fernanda
|
|
2001
|
41 |
11 |
p. 1809-1813
5 p.
|
article
|
| 10 |
Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits
|
Wang, Yu
|
|
2001
|
41 |
11 |
p. 1781-1787
7 p.
|
article
|
| 11 |
Impact of interface nature on deep sub-micron Al-plug resistance
|
Tsui, Bing-Yue
|
|
2001
|
41 |
11 |
p. 1889-1896
8 p.
|
article
|
| 12 |
Influence of device geometry on SOI single-hole transistor characteristics
|
Tang, X
|
|
2001
|
41 |
11 |
p. 1841-1846
6 p.
|
article
|
| 13 |
Layout and bias options for maximizing V t1 in cascoded NMOS output buffers
|
Miller, James W.
|
|
2001
|
41 |
11 |
p. 1751-1760
10 p.
|
article
|
| 14 |
Lead-free plastic area array BGAs and polymer stud grid arraysTM package reliability
|
Wojciechowski, Dominique
|
|
2001
|
41 |
11 |
p. 1829-1839
11 p.
|
article
|
| 15 |
[No title]
|
Mergens, Markus P.J
|
|
2001
|
41 |
11 |
p. 1737-
1 p.
|
article
|
| 16 |
Novel fully silicided ballasting and MFT design techniques for ESD protection in advanced deep sub-micron CMOS technologies
|
Verhaege, Koen G
|
|
2001
|
41 |
11 |
p. 1739-1749
11 p.
|
article
|
| 17 |
On the InGaP/In x Ga1−x As pseudomorphic high electron-mobility transistors for high-temperature operations
|
Lin, Kun-Wei
|
|
2001
|
41 |
11 |
p. 1897-1902
6 p.
|
article
|
| 18 |
Study of the self-alignment of no-flow underfill for micro-BGA assembly
|
Chan, Y.C
|
|
2001
|
41 |
11 |
p. 1867-1875
9 p.
|
article
|
| 19 |
The development of poled polyimide dielectric layers for simultaneous testing and light guiding applications in MCM-Ds
|
Mechtel, D.M
|
|
2001
|
41 |
11 |
p. 1847-1855
9 p.
|
article
|
| 20 |
The importance of standardizing CDM ESD test head parameters to obtain data correlation
|
Henry, Leo G.
|
|
2001
|
41 |
11 |
p. 1789-1800
12 p.
|
article
|
| 21 |
Tools for contactless testing and simulation of CMOS circuits
|
Stellari, F
|
|
2001
|
41 |
11 |
p. 1801-1808
8 p.
|
article
|
Journal description