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Details for article 20 of 23 found articles
| Title: |
Modeling and Verification of Interface and Bulk Trap Level Density Extraction in SONOS Memory Charge Trapping Layer |
| Author: |
Nam, Ki-Ryung Jeong, Jun-Kyo Sung, Jae-Young Lee, Ga-Won |
| Appeared in: |
Transactions on electrical and electronic materials |
| Paging: | Volume 22 () nr. 3 pages 372-377 |
| Year: |
2021-04-27 |
| Contents: | |
| Publisher: |
The Korean Institute of Electrical and Electronic Material Engineers (KIEEME), Seoul |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 20 of 23 found articles
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