|
| << vorige | volgende >> |
Tijdschrift beschrijving
Alle jaargangen van het bijbehorende tijdschrift
Alle afleveringen van het bijbehorende jaargang
Alle artikelen van de bijbehorende aflevering
Details van artikel 4 van 5 gevonden artikelen
| Titel: |
Pipelining Architecture of AES Encryption and Key Generation with Search Based Memory |
| Auteur: |
Subashri T Arunachalam R Gokul Vinoth Kumar B Vaidehi V |
| Verschenen in: |
International journal of VLSI design & communication systems (VLSICS) |
| Paginering: | Jaargang 1 (2010) nr. 4 pagina's 48-60 |
| Jaar: |
2010 |
| Inhoud: |
A high speed security algorithm is always important for wired/wireless environment. The symmetric block cipher plays a major role in the bulk data encryption. One of the best existing symmetric security algorithms to provide data security is AES. AES has the advantage of being implemented in both hardware and software. Hardware implementation of the AES has the advantage of increased throughput and offers better security. Search based S-box architecture has been proposed in this paper to reduce the constraint in the hardware resources. The pipelined architecture of the AES algorithm is proposed in order to increase the throughput of the algorithm. Moreover the key schedule algorithm of the AES encryption is pipelined to get the speedup. |
| Uitgever: |
Academy & Industry Research Collaboration Center (AIRCC) (provided by DOAJ) |
| Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
Details van artikel 4 van 5 gevonden artikelen
| << vorige | volgende >> |