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Details van artikel 38 van 49 gevonden artikelen
| Titel: |
Performance Analysis of a 32-Bit Multiplier with a Carry-Look-Ahead Adder and a 32-bit Multiplier with a Ripple Adder using VHDL |
| Auteur: |
Hasan Krad Aws Yousif Al-Taie |
| Verschenen in: |
Journal of computer science |
| Paginering: | Jaargang 4 (2008) nr. 4 pagina's 305-308 |
| Jaar: |
2008 |
| Inhoud: |
This study presents a performance analysis of two different multipliers for unsigned data, one uses a carry-look-ahead adder and the second one uses a ripple adder. The study’s main focus is onthe speed of the multiplication operation on these 32-bit multipliers which are modeled using VHDL, A hardware description language. The multiplier with a carry-look-ahead adder has shown a betterperformance over the multiplier with a ripple adder in terms of gate delays. Under the worst case, the multiplier with the fast adder shows approximately twice the speed of the multiplier with the rippleadder. The multiplier with a ripple adder uses time = 979.056 ns, while the multiplier with the carrylook- ahead adder uses time = 659.292 ns. |
| Uitgever: |
Science Publications (provided by DOAJ) |
| Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
Details van artikel 38 van 49 gevonden artikelen
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