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Details van artikel 21 van 46 gevonden artikelen
| Titel: |
Hardware Implementation of Hybrid Dynamic Voltage Scaling |
| Auteur: |
R. Seshasayanan S.K. Srivatsa |
| Verschenen in: |
Information technology journal |
| Paginering: | Jaargang 6 (2007) nr. 3 pagina's 338-344 |
| Jaar: |
2007 |
| Inhoud: |
The research presented in this study addresses reducing the power consumption of processor by adjusts the clock speed and voltage dynamically for hard real time tasks. The energy efficiency of a DVS algorithm largely depends on the performance of the slack estimation method used in it. The approach uses fixed priorities assigned tasks. It targets energy consumption reduction by using both on-line and off-line decisions, taken both at task level and at task-set level. We consider sets of independent tasks running on processors with dynamic voltage and frequency scaling techniques, where every deadline has to be met. Here we consider a few sets of independent tasks running on processor with dynamic frequency and voltage scaling. By using Hybrid DVS algorithm, the power savings is obtained. The efficient inter and intra algorithms are implemented in VHDL. The simulation and synthesize report are shown. By using this approach we achieve energy reductions. |
| Uitgever: |
Asian Network for Scientific Information (provided by DOAJ) |
| Bronbestand: |
Elektronische Wetenschappelijke Tijdschriften |
Details van artikel 21 van 46 gevonden artikelen
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