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Details for article 7 of 12 found articles
| Title: |
Design of a testing fixture for printed circuit boards |
| Author: |
Ahmadi, Reza H. Kouvelis, Panagiotis |
| Appeared in: |
IIE transactions |
| Paging: | Volume 27 (1995) nr. 1 pages 81-89 |
| Year: |
1995-02-01 |
| Contents: |
In this paper we discuss a functional testing problem in the printed circuit card assembly environment. The testing problem the design engineer faces is the following: Assign the maximum number of 100 mil (1 mil = 10-3 inch) probes to an appropriately selected set of 50 mil pads in a way that avoids the creation of short circuits or other imposed engineering constraints. Once the above assignment problem is solved, a testing fixture that holds the 100 mil probes at their appropriate positions is constructed. We are addressing the design problem of the above mentioned testing fixture. An integer programming formulation of the problem is presented. A hierarchical decomposition scheme, which at a first level specifies the subset of 50 mil pads to be tested, and at a second level decides on the allocation of a 100 or 50 mil probes to the tested pads, exhibits a near optimal performance for most cases of practical interest. The first-level problem can be solved in polynomial time with a greedy procedure. The second-level problem is equivalent to node packing. For a special class of sparse graphs encountered in our application a simple greedy algorithm optimally solves the corresponding node packing problem. |
| Publisher: |
Taylor & Francis |
| Source file: |
Elektronische Wetenschappelijke Tijdschriften |
Details for article 7 of 12 found articles
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