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                                       Details for article 4 of 183 found articles
 
 
  A low damage Si3N4 sidewall spacer process for self-aligned sub-100nm III–V MOSFETs
 
 
Title: A low damage Si3N4 sidewall spacer process for self-aligned sub-100nm III–V MOSFETs
Author: Li, X.
Hill, R.J.W.
Zhou, H.
Wilkinson, C.D.W.
Thayne, I.G.
Appeared in: Microelectronic engineering
Paging: Volume 85 (2008) nr. 5-6 pages 4 p.
Year: 2008
Contents:
Publisher: Elsevier B.V.
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 4 of 183 found articles
 
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 Koninklijke Bibliotheek - National Library of the Netherlands