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                                       Details for article 2 of 13 found articles
 
 
  A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit
 
 
Title: A low active and leakage power SRAM using a read and write divided and BIST programmable timing control circuit
Author: Zhu, Jiafeng
Bai, Na
Wu, Jianhui
Appeared in: Microelectronics journal
Paging: Volume 44 (2013) nr. 4 pages 9 p.
Year: 2013
Contents:
Publisher: Elsevier Ltd
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 2 of 13 found articles
 
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