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                                       Details for article 30 of 37 found articles
 
 
  Sub-100 nm CMOS circuit performance with high-K gate dielectrics
 
 
Title: Sub-100 nm CMOS circuit performance with high-K gate dielectrics
Author: Mohapatra, N.R.
Dutta, A.
Sridhar, G.
Desai, M.P.
Rao, V.R.
Appeared in: Microelectronics reliability
Paging: Volume 41 (2001) nr. 7 pages 4 p.
Year: 2001
Contents:
Publisher: Elsevier Science Ltd
Source file: Elektronische Wetenschappelijke Tijdschriften
 
 

                             Details for article 30 of 37 found articles
 
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